- 1 Format of Message Address field and Message Data field
- 2 FSB Interrupt Message bus transaction
The method for the PCIe device to issue an MSI-X interrupt request is similar to the method for issuing an MSI interrupt request . Both write the data contained in the Message Data field to the address where the Message Address is located . MSI-X interrupts only mechanisms to support more interrupt request , is stored in a structure of MSI-X capablity point and a set of Message Address Message Data field is a pointer to a device can support PCIe MSI-X interrupt request is greater than the number of 32 , and the interrupt vector number is not required to be continuous. The set of Message Address and Message Data fields used by the MSI-X mechanism are stored in the BAR space of the PCIe device, rather than in the configuration space of the PCIe device, so that the user can determine the number of MSI-X interrupt requests.
When the system software initializes a PCIe device, if the PCIe device uses the MSI-X mechanism to transmit interrupt requests, it is necessary to set the Message Address and Message Data fields pointed to by the MSI-X Capability structure, and enable the MSI-X Enable bit. The implementation of x86 processors here is quite different from that of PowerPC processors.
In the x86 processor system , the PCIe device also implements the MSI/MSI-X mechanism by writing the value specified by the Message Data to the Message Address . In an x86 processor system, the Message Adress field and Message Data field used by PCIe devices are different from the PowerPC processor.
In the x86 processor system, the Message Address field used by the PCIe device still stores the PCI bus domain address, and its format is shown in Figure 6-7.
Among them, the 31st to 20th bits store the base address of the FSB Interrupts memory space , and its value is 0xFEE. When the PCIe device writes the address space of the "PCI bus domain" 0xFEEX-XXXX, the MCH/ICH will first perform the address conversion from "PCI bus domain" to "memory domain", and then translate this write operation into The Interrupt Message bus transaction of the FSB bus, thereby submitting an interrupt request to the CPU core.
The x86 processor uses the FSB Interrupt Message bus transaction to forward MSI/MSI-X interrupt requests . The advantage of using this method is that while submitting the interrupt request to the CPU core, the interrupt vector used by the PCIe device is submitted, so that the CPU does not need to use the interrupt response cycle to obtain the interrupt vector from the register. A detailed description of the FSB Interrupt Message bus transaction is shown below.
The meanings of other bits in the Message Address field are as follows.
- The Destination ID field stores the ID number of the target CPU. When the ID of the target CPU is equal to this field, the target CPU will receive this Interrupt Message. The FSB Interrupt Message bus transaction can submit interrupt requests to different CPUs.
- When the RH (Redirection Hint Indication) bit is 0, it means that the Interrupt Message will be sent directly to the target CPU with the same Destination ID field; if RH is 1, the interrupt forwarding function will be enabled.
- The DM (Destination Mode) bit indicates whether the Destination ID field is translated into Logical or Physical APIC ID when delivering the interrupt request with the lowest priority. There are three modes of APIC ID in x86 processors, namely Physical, Logical and Cluster ID modes.
- If the RH bit is 1 and the DM bit is 0, the Destination ID field uses the Physical mode; if the RH bit is 1 and the DM bit is 1, the Destination ID field uses the Logical mode; if the RH bit is 0, the DM bit will be ignored.
The description of these fields above is related to the APIC interrupt controller used by x86 processors. The detailed description of APIC is beyond the scope of this book. Readers who are interested in this part can refer to Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A: System Programming Guide, Part 1.
Unlike the MPC8572 processor that processes MSI interrupt requests, the x86 processor uses the Interrupt Message bus transaction of the FSB to process the MSI/MSI-X interrupt requests of PCIe devices . As shown above, when the MPC8572 processor processes the MSI interrupt request, the MPIC interrupt controller first intercepts the MSI interrupt request, then the MPIC interrupt controller submits the interrupt request to the CPU, and the CPU interrupts the controller from the MPIC interrupt controller through the interrupt response cycle The interrupt vector is obtained from the ACK register.
The main problem with this approach is that when there are multiple CPUs in a processor, these CPUs need to obtain the interrupt vector from the ACK register of the MPIC interrupt controller through the interrupt response cycle. In an interrupt-intensive application, the ACK register is likely to become a system bottleneck. The use of Interrupt Message bus transaction can effectively avoid this system bottleneck, because in this way the interrupt information and interrupt vector will reach the designated CPU at the same time, without the need to use the interrupt response cycle to obtain the interrupt vector.
The x86 processor also has a method of submitting MSI/MSI-X interrupt requests through the interrupt controller. There is a "The IRQ Pin Assertion Register" register in the I/O APIC, the register address is 0xFEC00020 (the register is in the memory domain and PCI bus The address in the domain is 0xFEC00020), and the 4th to 0th bits store the IRQ Number. The system software can set the Message Address register of the PCIe device to 0xFEC00020 and the Meaasge Data register to the corresponding IRQ Number.
When the PCIe device needs to submit an MSI interrupt request, it will write the data in the Message Data register to the 0xFEC00020 address of the PCI bus domain. At this time, this memory write request writes the data into The IRQ Pin Assertion Register of I/O APIC, and the I/O APIC will finally send this MSI interrupt request to the Local APIC, and then the Local APIC will pass the INTR# signal to the CPU. Submit an interrupt request.
The above steps are similar to how the MPC8572 processor transmits MSI interrupts. In x86 processors, this approach has basically been abandoned. The following takes Figure 6-9 as an example to illustrate how the x86 processor uses the Interrupt Message bus transaction of the FSB bus to submit an MSI/MSI-X interrupt request to the CPU.
Before the PCIe device sends the MSI/MSI-X interrupt request, the system software needs to reasonably set the PCIe device MSI/MSI-X Capability register so that the value of the Message Address register is 0xFEExx00y (where xx represents the APIC ID and y is RH+DM) , And reasonably set the Vector field of the Message Data register .
When a PCIe device submits an MSI/MSI-X interrupt request, it needs to write the data contained in the Message Data register to the address 0xFEExx00y, and send it to the RC in the form of a memory write TLP. If the ICH receives this memory write TLP, it will submit this TLP to the MCH through the DMI interface. After receiving the TLP, the MCH finds that the destination address of the TLP is in the FSB Interrupts memory space, and converts the memory write request of the PCIe bus into an Interrupt Message bus transaction, and broadcasts it on the FSB bus.
The CPU on the FSB bus, according to the APIC ID information, chooses whether to receive the Interrupt Message bus transaction and enters the interrupt state. After that, the CPU will directly obtain the interrupt vector number from the bus transaction and execute the corresponding interrupt service routine. The interrupt vector needs to be obtained from the APIC interrupt controller. Compared with the MPIC interrupt controller of the PowerPC processor, this method has more advantages.